Combination Lock

I have a long standing desire post my school work online. There are a couple reasons for this:

  • I usually work too long and too hard to just turn it in to teacher
  • I believe that by posting my work, I will help others

There is always the concern that someone may just cold spike it1, but I think the benefits are clearly present.

Now a slight tangent on “cold spiking.” I just now looked it up on Urban Dictionary:
From www.urbandictionary.com:

cold spike

To copy homework with no understanding of how to do it. Typically accomplished in the 10 minutes before said homework is due.

Originates from the Colorado School of Mines, where cold spiking is so revered that every year they award a prize for the best spiker.

Hey Jeremy! Let me cold spike your thermo or I’ll beat you bloody.
by Spjorkster Mar 10, 2005

A couple thoughts: I don’t know who “Spjorkster” is. I don’t cold spike; it’s stupid and I rather not turn in the homework. The term has been around since at least 2005, that’s amazing.

So now the project. The object reads:

The objective of this take-home project is to design and implement an electronic combination lock. The combination lock is to have a start-up combination code of 1-2-3-4 that MUST be changed immediately upon first-time activation. Furthermore, if the new combination code has three numbers all the same then an error message is to be sent and a different code has to be entered as the combination. Each number in the four-number combination code is to be an eight-bit vector.

The requirements are thus:

The combination lock design MUST be implemented as a state machine (using VHDL), with a minimum of three states: open, lock, set_combo. More that three states may be used (may or may not require greater than 3 states). The outputs should include a lock signal, indicating that the lock is currently locked, an open signal indicating that the lock is currently unlocked. The data inputs are to include the combination code (for when setting a new unlock code.) Additional there is to be a mechanism for resetting the entire circuit. Plus your design is to handle the succession of three wrong guesses at the combination by going into a security mode in which the initial code (1-2-3-4) followed by the entry of the correct code is required to unlock the lock. In your simulation waveforms, you MUST display the state variable (this will display the states traversed in setting, locking and unlocking the combination) along with the inputs and outputs.

There must also be at least four cases in which the combination is incorrect and at least three cases in which the combination is correct. And there is to be a string of three consecutive wrong attempts to unlock putting the circuit in the the security mode in which the initial code (1-2-3-4) immediately followed by the entry of the correct code is required to unlock the lock Remember to include in your report all schematics and/or VHDL code, simulation waveforms and state diagram/table.

Doing this all in VHDL isn’t as painful as I thought, but it was still very painful. I think the only thing I hated programing more so far was threaded tasks in Java. The idea of using states is somewhat similar, but not the same functionally.

Here’s the plan in a nutshell:

Yes, I did that state diagram. Isn’t it pretty?

Here’s the code:

<br />
LIBRARY ieee;<br />
USE ieee.std_logic_1164.all;<br />
USE IEEE.STD_LOGIC_ARITH.all;<br />
USE IEEE.STD_LOGIC_UNSIGNED.ALL;</p>
<p>ENTITY combinationLock IS<br />
	PORT(	Clock, Reset		: IN		STD_LOGIC; -- use positive logic for the reset<br />
			w					: IN		STD_LOGIC_VECTOR (1 DOWNTO 0); -- user action: 00 is no action; 01 is action; 11 is lock<br />
			a					: IN		STD_LOGIC_VECTOR (7 DOWNTO 0); -- digit a input<br />
			b					: IN		STD_LOGIC_VECTOR (7 DOWNTO 0); -- digit b input<br />
			c					: IN		STD_LOGIC_VECTOR (7 DOWNTO 0); -- digit c input<br />
			d					: IN		STD_LOGIC_VECTOR (7 DOWNTO 0); -- digit d input<br />
			aCode				: BUFFER	STD_LOGIC_VECTOR (7 DOWNTO 0); -- code of the first digit<br />
			bCode				: BUFFER	STD_LOGIC_VECTOR (7 DOWNTO 0); -- code of the second digit<br />
			cCode				: BUFFER	STD_LOGIC_VECTOR (7 DOWNTO 0); -- code of the third digit<br />
			dCode				: BUFFER	STD_LOGIC_VECTOR (7 DOWNTO 0); -- code of the fourth digit<br />
			unlockAttempt		: BUFFER	STD_LOGIC_VECTOR (1 DOWNTO 0); -- to keep track of how many attmpts have been made to unlock<br />
			isLock				: OUT		STD_LOGIC; -- is the safe locked<br />
			isError				: OUT		STD_LOGIC); -- is there error -- both lights on indicate in combo setting mode!<br />
END combinationLock;</p>
<p>ARCHITECTURE Behavior OF combinationLock IS<br />
	TYPE State_type IS(SET_COMBO, LOCK_OPEN, LOCK_SECURE, SECURITY_MODE);<br />
	SIGNAL y : State_type;</p>
<p>BEGIN<br />
	PROCESS( Reset, Clock)<br />
	BEGIN<br />
		IF Reset = '1' THEN<br />
			aCode &lt;= CONV_STD_LOGIC_VECTOR(1,8);<br />
			bCode &lt;= CONV_STD_LOGIC_VECTOR(2,8);<br />
			cCode &lt;= CONV_STD_LOGIC_VECTOR(3,8);<br />
			dCode &lt;= CONV_STD_LOGIC_VECTOR(4,8);<br />
			y &lt;= SET_COMBO;<br />
		ELSIF (Clock'EVENT AND Clock = '1') THEN<br />
			CASE y IS<br />
				WHEN SET_COMBO =&gt;<br />
					IF (w(1) = '0' AND w(0) = '0') THEN<br />
						y &lt;= SET_COMBO;<br />
					ELSIF (w(1) = '0' AND w(0) = '1') THEN<br />
						IF ( ( (a = b) AND (b = c) ) OR ( (a = c) AND (c = d) ) OR ( (a = b) AND (b = d) ) OR ( (b = c) AND (c = d) ) )THEN -- three numbers are repeated -- -----<br />
							isError &lt;= '1';<br />
							y &lt;= SET_COMBO;<br />
						ELSE -- program new code<br />
							aCode &lt;= a;<br />
							bCode &lt;= b;<br />
							cCode &lt;= c;<br />
							dCode &lt;= d;<br />
							isError &lt;= '0';<br />
							y &lt;= LOCK_OPEN;<br />
						END IF;<br />
					END IF;</p>
<p>				WHEN LOCK_OPEN =&gt;<br />
					isLock &lt;= '0';<br />
					unlockAttempt &lt;= CONV_STD_LOGIC_VECTOR(0,2); -- reset the security lockout<br />
					IF (w(1) = '0' AND w(0) = '0') THEN<br />
						y &lt;= LOCK_OPEN;<br />
					ELSIF (w(1) = '0' AND w(0) = '1') THEN<br />
						y &lt;= SET_COMBO;<br />
					ELSIF (w(1) = '1' AND w(0) = '1') THEN<br />
						y &lt;= LOCK_SECURE;<br />
					END IF;</p>
<p>				WHEN LOCK_SECURE =&gt;<br />
					isLock &lt;= '1'; -- set the lock indicator<br />
					isError &lt;= '0'; -- clear all errors because it's locked now</p>
<p>					IF (w(1) = '0' AND w(0) = '0') THEN<br />
						y &lt;= LOCK_SECURE;</p>
<p>					ELSIF ( w(1) = '0' AND w(0) = '1') THEN</p>
<p>						IF (unlockAttempt = CONV_STD_LOGIC_VECTOR(0,2) ) THEN</p>
<p>							IF (a = aCode AND b = bCode AND c = cCode AND d = dCode) THEN<br />
								y &lt;= LOCK_OPEN;<br />
							ELSE<br />
								unlockAttempt &lt;= CONV_STD_LOGIC_VECTOR(1,2);<br />
								y &lt;= LOCK_SECURE;<br />
							END IF;</p>
<p>						ELSIF (unlockAttempt = CONV_STD_LOGIC_VECTOR(1,2) ) THEN</p>
<p>							IF (a = aCode AND b = bCode AND c = cCode AND d = dCode) THEN<br />
								y &lt;= LOCK_OPEN;<br />
							ELSE<br />
								unlockAttempt &lt;= CONV_STD_LOGIC_VECTOR(2,2);<br />
								y &lt;= LOCK_SECURE;<br />
							END IF;</p>
<p>						ELSIF (unlockAttempt = CONV_STD_LOGIC_VECTOR(2,2) ) THEN</p>
<p>							IF (a = aCode AND b = bCode AND c = cCode AND d = dCode) THEN<br />
								y &lt;= LOCK_OPEN;<br />
							ELSE<br />
								unlockAttempt &lt;= CONV_STD_LOGIC_VECTOR(3,2);<br />
								y &lt;= SECURITY_MODE;<br />
							END IF;</p>
<p>						ELSIF (unlockAttempt = CONV_STD_LOGIC_VECTOR(3,2)) THEN<br />
								y &lt;= SECURITY_MODE;<br />
						END IF;<br />
					END IF;</p>
<p>				WHEN SECURITY_MODE =&gt;<br />
					IF (w(1) = '0' AND w(0) = '0') THEN<br />
						y &lt;= SECURITY_MODE;<br />
					ELSIF (w(1) = '0' AND w(0) = '1') THEN<br />
						IF(a = CONV_STD_LOGIC_VECTOR(1,8) AND b = CONV_STD_LOGIC_VECTOR(2,8) AND c = CONV_STD_LOGIC_VECTOR(3,8) AND d = CONV_STD_LOGIC_VECTOR(4,8)) THEN<br />
							unlockAttempt &lt;= CONV_STD_LOGIC_VECTOR(2,2);<br />
							y &lt;= LOCK_SECURE;<br />
						END IF;<br />
					END IF;</p>
<p>			END CASE;<br />
		END IF;<br />
	END PROCESS;<br />
END Behavior;<br />

In all states (except Reset, which isn’t defined as typical state), ’00’ is used to stay within the state. ’01’ is used as an action key and ’11’ is used to lock the device (as noted with comments within the VHDL code). isError is ‘1’ when a user has entered a new invalid combination (any combination with where 3 digits are the same). Security Mode is entered when three unsuccessful attempts have been made to unlock the device. When this happens, the Security Mode-state is entered and the user must enter ‘1 2 3 4’. When this happens, the user is sent back to the Lock Secure-state and is granted one try before being kicked back to the Security Mode-state. However, if the attempt is correct, the user is sent to the Lock Open-state where they can change the combination or lock the device again.

Here’s the schematic:
schematic.PNG

…and the waveforms, which shows that it does indeed work:

waveform_0us.PNG
waveform_2us.PNG
waveform_4us.PNG
waveform_6us.PNG

Note: realACode, realBCode, realCCode, realDCode, realUnlock[1] and realUnlock[0] are debugging variables used to ensure that the device is working properly during testing. real*Code is used to display the stored combination code and realUnlock[*] is used to count how many attempts have been tried to unlock the device.

All in all, pretty cool. Minus the nine hours or so it took to do it.

1 Amanda turned me on to this phrase.