Final Grades

Grades for this semester are in. Drum roll please:

Fluid Mechanics: B
Digital Logic: A
Advanced Engineering Math: B
Information Systems: D
Engineering Circuit Analysis: B

GPA for this semester: 2.875
Cumulative GPA: 2.615

This brings me to 94.5 earned hours which officially makes me a senior. Three more semester left.

Sick and Finals

I’m come down with a rather nasty cold (or something, crossing my fingers for cold though). It’s been really bad today and yesterday, so I’m hoping that I’m reaching the peak of this thing and will be back in full force for next week.

Next week also happens to be the last week of school before finals. Four days of school, Friday off, and then finals on Saturday, Monday and Wednesday.

I think the good news about finals is that two of my classes are going to be 100% take home finals (Digital Logic and Engineering Circuit Analysis). Advanced Engineering Math is also going to have a take home section.

Combination Lock

I have a long standing desire post my school work online. There are a couple reasons for this:

  • I usually work too long and too hard to just turn it in to teacher
  • I believe that by posting my work, I will help others

There is always the concern that someone may just cold spike it1, but I think the benefits are clearly present.

Now a slight tangent on “cold spiking.” I just now looked it up on Urban Dictionary:
From www.urbandictionary.com:

cold spike

To copy homework with no understanding of how to do it. Typically accomplished in the 10 minutes before said homework is due.

Originates from the Colorado School of Mines, where cold spiking is so revered that every year they award a prize for the best spiker.

Hey Jeremy! Let me cold spike your thermo or I’ll beat you bloody.
by Spjorkster Mar 10, 2005

A couple thoughts: I don’t know who “Spjorkster” is. I don’t cold spike; it’s stupid and I rather not turn in the homework. The term has been around since at least 2005, that’s amazing.

So now the project. The object reads:

The objective of this take-home project is to design and implement an electronic combination lock. The combination lock is to have a start-up combination code of 1-2-3-4 that MUST be changed immediately upon first-time activation. Furthermore, if the new combination code has three numbers all the same then an error message is to be sent and a different code has to be entered as the combination. Each number in the four-number combination code is to be an eight-bit vector.

The requirements are thus:

The combination lock design MUST be implemented as a state machine (using VHDL), with a minimum of three states: open, lock, set_combo. More that three states may be used (may or may not require greater than 3 states). The outputs should include a lock signal, indicating that the lock is currently locked, an open signal indicating that the lock is currently unlocked. The data inputs are to include the combination code (for when setting a new unlock code.) Additional there is to be a mechanism for resetting the entire circuit. Plus your design is to handle the succession of three wrong guesses at the combination by going into a security mode in which the initial code (1-2-3-4) followed by the entry of the correct code is required to unlock the lock. In your simulation waveforms, you MUST display the state variable (this will display the states traversed in setting, locking and unlocking the combination) along with the inputs and outputs.

There must also be at least four cases in which the combination is incorrect and at least three cases in which the combination is correct. And there is to be a string of three consecutive wrong attempts to unlock putting the circuit in the the security mode in which the initial code (1-2-3-4) immediately followed by the entry of the correct code is required to unlock the lock Remember to include in your report all schematics and/or VHDL code, simulation waveforms and state diagram/table.

Doing this all in VHDL isn’t as painful as I thought, but it was still very painful. I think the only thing I hated programing more so far was threaded tasks in Java. The idea of using states is somewhat similar, but not the same functionally.

Here’s the plan in a nutshell:

Yes, I did that state diagram. Isn’t it pretty?

Here’s the code:

LIBRARY ieee;	
USE ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY combinationLock IS
	PORT(	Clock, Reset		: IN		STD_LOGIC; -- use positive logic for the reset
			w					: IN		STD_LOGIC_VECTOR (1 DOWNTO 0); -- user action: 00 is no action; 01 is action; 11 is lock
			a					: IN		STD_LOGIC_VECTOR (7 DOWNTO 0); -- digit a input
			b					: IN		STD_LOGIC_VECTOR (7 DOWNTO 0); -- digit b input
			c					: IN		STD_LOGIC_VECTOR (7 DOWNTO 0); -- digit c input
			d					: IN		STD_LOGIC_VECTOR (7 DOWNTO 0); -- digit d input
			aCode				: BUFFER	STD_LOGIC_VECTOR (7 DOWNTO 0); -- code of the first digit
			bCode				: BUFFER	STD_LOGIC_VECTOR (7 DOWNTO 0); -- code of the second digit
			cCode				: BUFFER	STD_LOGIC_VECTOR (7 DOWNTO 0); -- code of the third digit
			dCode				: BUFFER	STD_LOGIC_VECTOR (7 DOWNTO 0); -- code of the fourth digit
			unlockAttempt		: BUFFER	STD_LOGIC_VECTOR (1 DOWNTO 0); -- to keep track of how many attmpts have been made to unlock
			isLock				: OUT		STD_LOGIC; -- is the safe locked
			isError				: OUT		STD_LOGIC); -- is there error -- both lights on indicate in combo setting mode!
END combinationLock;

ARCHITECTURE Behavior OF combinationLock IS
	TYPE State_type IS(SET_COMBO, LOCK_OPEN, LOCK_SECURE, SECURITY_MODE);
	SIGNAL y : State_type;
	
BEGIN
	PROCESS( Reset, Clock)
	BEGIN
		IF Reset = '1' THEN
			aCode <= CONV_STD_LOGIC_VECTOR(1,8);
			bCode <= CONV_STD_LOGIC_VECTOR(2,8);
			cCode <= CONV_STD_LOGIC_VECTOR(3,8);
			dCode <= CONV_STD_LOGIC_VECTOR(4,8);
			y <= SET_COMBO;
		ELSIF (Clock'EVENT AND Clock = '1') THEN
			CASE y IS
				WHEN SET_COMBO =>
					IF (w(1) = '0' AND w(0) = '0') THEN
						y <= SET_COMBO;
					ELSIF (w(1) = '0' AND w(0) = '1') THEN
						IF ( ( (a = b) AND (b = c) ) OR ( (a = c) AND (c = d) ) OR ( (a = b) AND (b = d) ) OR ( (b = c) AND (c = d) ) )THEN -- three numbers are repeated -- ----- 
							isError <= '1';
							y <= SET_COMBO;
						ELSE -- program new code
							aCode <= a;
							bCode <= b;
							cCode <= c;
							dCode <= d;
							isError <= '0';
							y <= LOCK_OPEN;
						END IF;
					END IF;
								
				WHEN LOCK_OPEN =>
					isLock <= '0';
					unlockAttempt <= CONV_STD_LOGIC_VECTOR(0,2); -- reset the security lockout
					IF (w(1) = '0' AND w(0) = '0') THEN
						y <= LOCK_OPEN;
					ELSIF (w(1) = '0' AND w(0) = '1') THEN
						y <= SET_COMBO;
					ELSIF (w(1) = '1' AND w(0) = '1') THEN
						y <= LOCK_SECURE;
					END IF;
				
				WHEN LOCK_SECURE =>
					isLock <= '1'; -- set the lock indicator
					isError <= '0'; -- clear all errors because it's locked now
					

					
					IF (w(1) = '0' AND w(0) = '0') THEN
						y <= LOCK_SECURE;

					ELSIF ( w(1) = '0' AND w(0) = '1') THEN
						
						IF (unlockAttempt = CONV_STD_LOGIC_VECTOR(0,2) ) THEN
						
							IF (a = aCode AND b = bCode AND c = cCode AND d = dCode) THEN
								y <= LOCK_OPEN;
							ELSE
								unlockAttempt <= CONV_STD_LOGIC_VECTOR(1,2);
								y <= LOCK_SECURE;
							END IF;
							
						ELSIF (unlockAttempt = CONV_STD_LOGIC_VECTOR(1,2) ) THEN
						
							IF (a = aCode AND b = bCode AND c = cCode AND d = dCode) THEN
								y <= LOCK_OPEN;
							ELSE
								unlockAttempt <= CONV_STD_LOGIC_VECTOR(2,2);
								y <= LOCK_SECURE;
							END IF;
						
						ELSIF (unlockAttempt = CONV_STD_LOGIC_VECTOR(2,2) ) THEN
						
							IF (a = aCode AND b = bCode AND c = cCode AND d = dCode) THEN
								y <= LOCK_OPEN;
							ELSE
								unlockAttempt <= CONV_STD_LOGIC_VECTOR(3,2);
								y <= SECURITY_MODE;
							END IF;
							
						ELSIF (unlockAttempt = CONV_STD_LOGIC_VECTOR(3,2)) THEN
								y <= SECURITY_MODE;
						END IF;
					END IF;
						
				
				WHEN SECURITY_MODE =>
					IF (w(1) = '0' AND w(0) = '0') THEN
						y <= SECURITY_MODE;
					ELSIF (w(1) = '0' AND w(0) = '1') THEN
						IF(a = CONV_STD_LOGIC_VECTOR(1,8) AND b = CONV_STD_LOGIC_VECTOR(2,8) AND c = CONV_STD_LOGIC_VECTOR(3,8) AND d = CONV_STD_LOGIC_VECTOR(4,8)) THEN
							unlockAttempt <= CONV_STD_LOGIC_VECTOR(2,2);
							y <= LOCK_SECURE;
						END IF;							
					END IF;
			
			END CASE;
		END IF;
	END PROCESS;
END Behavior;

In all states (except Reset, which isn’t defined as typical state), ’00’ is used to stay within the state. ’01’ is used as an action key and ’11’ is used to lock the device (as noted with comments within the VHDL code). isError is ‘1’ when a user has entered a new invalid combination (any combination with where 3 digits are the same). Security Mode is entered when three unsuccessful attempts have been made to unlock the device. When this happens, the Security Mode-state is entered and the user must enter ‘1 2 3 4’. When this happens, the user is sent back to the Lock Secure-state and is granted one try before being kicked back to the Security Mode-state. However, if the attempt is correct, the user is sent to the Lock Open-state where they can change the combination or lock the device again.

Here’s the schematic:
schematic.PNG

…and the waveforms, which shows that it does indeed work:

waveform_0us.PNG
waveform_2us.PNG
waveform_4us.PNG
waveform_6us.PNG

Note: realACode, realBCode, realCCode, realDCode, realUnlock[1] and realUnlock[0] are debugging variables used to ensure that the device is working properly during testing. real*Code is used to display the stored combination code and realUnlock[*] is used to count how many attempts have been tried to unlock the device.

All in all, pretty cool. Minus the nine hours or so it took to do it.

1 Amanda turned me on to this phrase.

Busy

Things have been busy around here of late. This next week will be even harder.

AEM Exam tomorrow, Digital Logic Exam on Friday, Information Systems Exam a week from tomorrow.

I also fly out a week from tomorrow.

Fluids Project due on Thursday. Digital Logic take portion of exam due on Friday.

Fluids homework due Wednesday, Friday, and following Monday. Information Systems homework due Monday and Wednesday. Engineering Circuit Analysis homework due tomorrow and a week from tomorrow.

Then Thanksgiving.

Rockies World Series Ticket Clusterfucks

In case you haven’t heard, the Rockies are going to the world series after winning 20 of their last 21 games and sweeping both the Phillies and the Diamondbacks in the divisional playoffs.

To help makes things for the thousands of fans wanting tickets, the Colorado Rockies decided to only sell tickets online. Fair enough.

Well on Monday, millions of people attempted to buy tickets to the World Series at Coors Field. I was one of them. Using my tablet in the middle of Digital Logic, I was going to try and snag a couple of Rockpile tickets (Rockpile Tickets to the World Series: $65/each). Well, I sat there for about 10 minutes, a battle waged against server timeouts. I finally gave up.

The story reported later that night went something like this:
From colorado.rockies.mlb.com:

This morning, after more than 8.5 million hits on the Colorado Rockies website, Paciolan (Pack-ee-o-lan), Major League Baseball’s ticket vendor, experienced a system wide outage that impacted all of its North American customers. As a result, the Colorado Rockies have suspended the sale of 2007 World Series tickets scheduled to be played at Coors Field.

By this morning, the report had changed a bit. “System wide outage” turned into “external malicious attack” and eventually the Paciolan/MLB was playing the role of victim to a denial-of-service attack.

Yea, DOS my ass. Drew calls BS on this one and I have to agree with him:

From www.thedenverchannel.com:

Drew Curtis, the owner of Fark.com, called the denial of service claim “bogus.” Curtis, who has been on the receiving end of DOS attacks, told TheDenverChannel, “If they notified their upstream provider that they were under attack, the upstream provider could have shut that off in no time flat. They’re lying.”

Curtis said the heavy traffic Monday was likely coming from ticket brokers.

“Scalping is big money, big enough for scammers to develop utilities to open thousands of simultaneous connections attempting to buy tickets. I suspect that was at least part of the problem.”

Confident they’ve beefed up their network enough blocked the culprits, Rockies tickets went back on sale today at noon local time, kind of. I got on a campus computer1 at 11:45am and was online trying to get tickets until 1pm, when I had to leave for a meeting.

I spent wasted over an hour of time either looking at a 120 second countdown timer assuring me that the systems were under severe loads and I would be ushered in in the order I arrive or this screen:
timed_out.JPG

That screen, my friends, is a server timeout screen. In short, I was blocked again. Rocktober has frozen into Mocktober.

I looked for a report on a local news site saying that ticket sales would be suspended again because gremlins had been mucking around in the systems again; no such luck.

Tickets were selling, apparently. But at the appalling rate of 1500 per a minute.

So here’s what I don’t get. Pick any A-list music performer (U2, Dave Matthews Band, The Police, etc). Most of those performances sellout within minutes, like eight minutes. 60,000 tickets gone in a flash at a rate five times faster then Rockies were selling tickets. How come they never have any issues?

Let the scalping begin!

For more information on the squirrel with big nuts: http://www.fark.com/farq/about.shtml

1We sit on the FRGP Network, which, for the sake of this post, well call A Really Fast Connection™